1. Field of the Invention
The present invention relates to a sense amplifier, and more particularly, to a sense amplifier having an equalizer.
2. Background of the Related Art
In general, data stored at the memory cell are read out by means of a sense amplifier. Referring to FIG. 1, the operation of the conventional sense amplifier used in NOR type flash memories will be described.
A plurality of sense blocks 30 are connected to the bit lines (not shown), respectively. The sense amplifier 30 includes a sensing unit 10 for sensing data of the memory cell. The output SAIN of the sensing unit 10 is inputted to a non-inverting + terminal of a comparator SAO. The output SAINR of a reference voltage generator 20 having a reference cell is inputted to an inverting − terminal of the comparator SAO. For example, if the output SAIN of the sensing unit 10 is higher than the output SAINR of the reference voltage generator 20, the comparator SAO outputs a Low signal. On the contrary, if the output SAIN of the sensing unit 10 is lower than the output SAINR of the reference voltage generator 20, the comparator SAO output a High signal. In other words, if the memory cell is a program cell, the comparator SAO outputs a Low signal since the threshold voltage of the reference cell is lower than the threshold voltage of the memory cell. Meanwhile, if the memory cell is an erase cell, the comparator SAO outputs a High signal since the threshold voltage of the reference cell is higher than the threshold voltage of the memory cell.
FIG. 2 is a detailed circuit diagram of the sense amplifier shown in FIG. 1.
If a word line W/L is enabled and a bit line select signal YSEL and a program bar signal PGMb becomes a High level, transistors N7 and N6 are turned on. Also, if the sense enable bar signal SAENb is a Low level, a transistor P1 is turned on. For example, if the memory cell is a program cell, a transistor N5 is turned off since the output of an inverter INV3 becomes a Low level. Accordingly, as the power supply is outputted via the transistors P1 and N4, the output of the sensing unit 10 becomes a High level. The output of the comparator SAO is outputted via the inverters INV1 and INV2.
Meanwhile, if the word line W/L is enabled, a reference bit line select signal RYSEL becomes a High level and the reference program bar signal RPGMb becomes a High level, the transistors N2 and N3 are turned on. Also, if the sense enable bar signal SAENb is a Low level, the transistor P0 is turned on. As the reference cell is a program cell, the output of the inverter INV0 becomes the Low level and the transistor N1 is thus turned off. Accordingly, voltages dropped at the transistors P0 and N0 are outputted SAINR.
For example, if the output of the sensing unit 10 is higher than the output SAINR of the reference voltage generator 20, the comparator SAO outputs a Low signal. On the contrary, if the output of the sensing unit 10 is lower than the output SAINR of the reference voltage generator 20, the comparator SAO outputs a High signal. In other words, if the memory cell is a program cell, the comparator SAO outputs the Low signal since the threshold voltage of the reference cell is lower than the threshold voltage of the memory cell. If the memory cell is an erase cell, the comparator SAO outputs the High signal since the threshold voltage of the reference cell is higher than the threshold voltage of the memory cell. At this time, the output of the comparator SAO is outputted via the inverters INV1 and INV2.
The above operation of the sense amplifier is well illustrated in the timing diagram of FIG. 3. If an address transition signal ATD occurs as a result of sensing variations in the address during the periods T0 and T1 of FIG. 3, a voltage for read the word line is generated and then applied to the word lines. As it is required that a high word line voltage be generated at a low voltage operation, the word line voltage starts to increase with delayed time. However, the sense amplifier will be enabled at T1 if transition of the address occurs. As the word line voltage is not sufficiently raised, however, the outputs SAIN and SAINR are increased up to the T2 period. After this time period, as the reference cell is turned on and current thus flows, an adequate sensing operation occurs at T3 period. At this time, the output SAINR is rapidly increased since the load of the output SAINR is relatively lower than that of the output SAIN. Accordingly, time delay occurs until the sensing data is outputted after the word line turned on the memory cell and the reference cell. In other words, time when the output SAINR drops to the reference voltage, for example in case of a program cell, time when the output SAIN is raised after the bit line is charged makes the sensing speed slow.